Multiplierless, Reconfigurable Folded Architecture for VLSI Wavelet Filter

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Provided by: WSEAS
Topic: Hardware
Format: PDF
In this paper, the authors proposed the high-efficient and reconfigurable architectures for the 9/7-5/3 Discrete Wavelet Transform (DWT) based on convolution scheme. The proposed parallel and pipelined architectures consist of a High-pass Filter (HF) and a Low-pass Filter (LF). The critical paths of the proposed architectures are reduced. Filter coefficients of the biorthogonal 9/7-5/3 wavelet low-pass filter are quantized before implementation in the high-speed computation hardware. In the proposed architectures, all multiplications are performed using less shifts and additions.
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