Multithreaded Coprocessor Interface for Multi-Core Multimedia SoC

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Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
Modern architectures exploit task level parallelism to improve their performance in a cost-effective manner. However, task synchronization and management is time consuming and wastes computing resources especially on application-specific architectures, such as DSP. In this paper, the authors propose a smart coprocessor interface that helps to offload the task management job from MPU or DSP. In their simulations, their approach can improve the overall performance of a dual-core platform by 57%. The hardware overhead of the interface is only 1.56% of the DSP core.
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