Institute of Electrical & Electronic Engineers
As process variations get critical and integration scales evolve to billions of transistors in a single chip, timing closure of high complexity synchronous Integrated Circuits (ICs) becomes an increasingly complex task. Thus, asynchronous design techniques receive growing attention from the VLSI community. Currently, the most used circuit delay model for asynchronous design is the Quasi-Delay Insensitive (QDI), because it allows simpler timing closure and analysis and can be implemented using standard cell based approaches. Asynchronous paradigms are a way to deal with hard problems in newer technologies. Among the templates for ensuring efficient asynchronous design, Null Convention Logic (NCL) appears as a fast and relatively low area and power option, enabling semi-custom design.