Network on Chip: A New Approach of QoS Metric Modeling Based on Calculus Theory
According to ITRS, in 2018, ICs will be able to integrate billions of transistors, with feature sizes around 18 nm and clock frequencies near to 10 GHz. In this context, Network on Chip (NoC) appears as an attractive solution to implement future high performance networks and more QoS management. A NoC is composed by IP cores (Intellectual Propriety) and switches connected among themselves by communication channels. End-to-End Delay (EED) communication is accomplished by the exchange of data among IP cores. Often, the structure of particular messages is not adequate for the communication purposes. This leads to the concept of packet switching.