New Design of an RSFQ Parallel Multiplier Based on Booth Encoder

The authors will discuss the micro architecture, design, and testing of the first 8×8-bit (by modulo 256) parallel carry-save RSFQ multiplier implemented using the ISTEC10-kA/cm 21.0 um fabrication technology. Partial products area synchronously generated and sent to the reduction stage at the internal "Hardwired" rate of 80 GHz. The 8×8-bit RSFQ multiplier uses a two-level parallel carry save reduction tree that significantly reduces the multiplier latency. The 80-GHz carry-save reduction is implemented with asynchronous data driven wave-pipelined (4:2) compressors built with toggle flip-flop cells.

Provided by: International Journal On Intelligent Computer Electronic And Electrical (IJICEE) Topic: Hardware Date Added: Sep 2014 Format: PDF

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