New Design of Low Power 3T XOR Cell
The XOR gate forms the basic building blocks of various digital VLSI circuits like full adder, multiplier, comparator and parity checker. Enhancing the performance of the XOR gates can significantly improve the performance of the system as whole. This paper proposes a 3T XOR gate design implemented using pMOS transistors only. The design has been compared with existing design and significant improvement in power consumption has been obtained. All pre layout simulations are performed on 45nm standard model on Tanner EDA tool version 13.0.