New Noise Tolerant Domino Logic Circuits

In this paper, the authors propose four wide domino circuits to improve the robustness and reduce the power consumption. All proposed circuits use small potential at the source of the pull down network in the standby mode. Simulation is done using 90nm HSPICE for 32 input OR gate. Their proposed circuits reduce power consumption by 11.75% to 41.85%, improvement of unity noise gain by 41.03% to 90.87% and have better figure of merit as compared to conditional keeper domino.

Provided by: IDOSI Topic: Hardware Date Added: Sep 2014 Format: PDF

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