No Cache-Coherence: A Single-Cycle Ring Interconnection for Multi-Core L1-NUCA Sharing on 3D Chips

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Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
Consistent with the trend towards the use of many cores in SoC and 3D chip techniques, this paper proposes a \"Single-cycle ring\" interconnection (SC-Ring) with ultra-low latency and minimal complexity. The proposed SC-Ring allows multiple single-cycle transactions in parallel. The main features of the circuit-switched design include a set of 3-ported circuit switched routers (4-16) and a performance/timing effective arbiter. The arbiter, called \"BTPC\", features single-cycle arbitration and routing-control by means of the novel binary-tree paths convergence and path-prediction mechanisms, to provide a highly reduced time complexity.
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