NoC Traffic Monitoring for Billion Cycle Application Performance Debug Based on FPGA Platform
In this paper, a NoC traffic monitoring method is proposed for billion cycle application debug which help designer to improve system performance by the analysis of traffic distribution and balance through the network on chip. The hardware monitoring network consists of traffic collectors, which is reconfigurable to collect different traffic information such as packet latency and throughput. Designer can use this global traffic information from NoC traffic monitoring to tune the application task and data allocation and improve their application performance. A matrix multiplication test case illustrates the feasibility and potential performance improvement.