NOLO : A No-Loop, Predictive Useful Skew Methodology for Improved Timing in IC Implementation
Useful skew is a well-known design technique that adjusts clock sink latencies to improve performance and/or robustness of high-performance IC designs. Current design methodologies apply useful skew after the netlist has been synthesized (e.g., with a uniform skew or clock uncertainty assumption on all flops), and after placement has been performed. However, the useful skew optimization is constrained by the zero-skew assumptions that are baked into previous implementation steps. Previous paper of the researcher proposes to break this chickenegg quandary by back-annotating post-placement useful skews to a resynthesis step (and, this loop can be repeated several times).