Non-Uniform Power Access in Large Caches with Low-Swing Wires

Modern processors dedicate more than half their chip area to large L2 and L3 caches and these caches contribute significantly to the total processor power. A large cache is typically split into multiple banks and these banks are either connected through a bus (Uniform Cache Access - UCA) or an on-chip network (Non-Uniform Cache Access - NUCA). Irrespective of the cache model (NUCA or UCA), the complex interconnects that must be navigated within large caches are found to be the dominant part of cache access power.