International Journal of Engineering Research and Applications (IJERA)
In this paper, the authors describe the design of a 17 bit 4 stage pipelined Reduced Instruction Set Computer (RISC) processor using Verilog HDL in Xilinx. The processor implements the Harvard memory architecture, so the instruction and data memory spaces are both physically and logically separate. There is 5 bit opcode with totally 23 set of instructions. The CPU designed by using the pipelining and it will increase speed of processor with CPI=1. The pipeline stages such as fetch, decode, execute and store are used.