Novel Booth Encoder and Decoder for Parallel Multiplier Design
Fast multipliers are essential components of most VLSI applications like digital signal processing systems, microprocessors, etc. The speed of multiplier operation is of fastidious importance within the general-purpose processors. The essential multiplication principle is twofold i.e., evaluation of partial product and accumulation of the shifted partial products with the motivation to booth's algorithm. In this paper, an efficient design of modified booth encoder and decoder scheme for high performance of parallel multiplier has been proposed.