Novel Design of Dual Core RISC Architecture Implementation

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Provided by: Institute of Research and Journals (IRAJ)
Topic: Hardware
Format: PDF
In this paper, the authors proposed about simulation and synthesis of the 17bit RISC CPU based on MIPS (Microprocessor without Interlocked Pipeline Stage). RISC (Reduced Instruction Set Computing) is a style or family of processor architecture that share some characteristics and that has been designed to perform a small set of instructions. The most important feature of the RISC processor is that this processor is very simple and support load and store architecture. The design uses Harvard architecture which has distinct program memory space and data memory space. The design consists of four stages pipelining, which involves instruction fetch, instruction decode, execute and write back stage.
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