Provided by: International Journal of Advanced Research in Computer and Communication Engineering (IJARCCE)
In this paper, a new four bit reversible comparator circuit has been designed and was found that the proposed design is better in terms of no. of garbage outputs, no. of reversible logic gates used and no. of constants inputs than previous design. Reversible logic technology is becoming a very popular technology in the field of Nanoelectronics, low power chip design, and quantum circuits etc. The comparator design has been modeled and verified using VHDL and active-HDL 7.1 version.