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Design of shift registers opens the door for large memory than individual flip-flops. Shift registers are designed so as to support large sequential circuitry. The shift registers acts as temporary storage in the processor unit. The shift register, in this paper, is proposed with reversible logic gates. The Serial In Parallel Out (SIPO) shift register is implemented by connecting the RS flip-flop in serial order to feed the input and the output is extracted in the parallel order. Time delay of the reversible Shift register is much minimized in the order of 11.373 ns with the reduced power consumption of 203.27mW.