Provided by: International Journal of Advanced Research in Computer Science and Software Engineering (IJARCSSE)
A 1-V high-speed and low-power digital circuit technology with 0.5-pm Multi-Threshold CMOS (MT-CMOS) is proposed. This technology applies both low-threshold voltage and high-threshold voltage MOSFETs in one LSI. Low-threshold voltage MOSFETs enhances speed performance at a supply voltage of 1 V or less. High-threshold voltage MOSFETs suppresses the stand-by leakage current during the sleep period. The technology has achieved logic gate characteristics of 1.7-ns propagation delay time and 0.3-pWIMHzIgate power dissipation. To demonstrate its effectiveness, a standard cell based PLL-LSI was designed as a carrying vehicle. An 18-MHz operation at 1 V was obtained using a 0.5-pm MT-CMOS process.