Provided by: Association for Computing Machinery
Date Added: May 2014
The clock trees of high-performance synchronous circuits have many clock logic cells (e.g., clock gating cells, multiplexers and dividers) in order to achieve aggressive clock gating and required performance across a wide range of operating modes and conditions. As a result, clock tree structures have become very complex and difficult to optimize with automatic Clock Tree Synthesis (CTS) tools. In advanced process nodes, CTS becomes even more challenging due to On-Chip Variation (OCV) effects. In this paper, the authors present a new CTS methodology that optimizes clock logic cell placements and buffer insertions in the top level of a clock tree. They formulate the top-level clock tree optimization problem as a linear program that minimizes a weighted sum of timing slacks, clock uncertainty and wirelength.