OE+IOE: A Novel Turn Model Based Fault Tolerant Routing Scheme for Networks-on-Chip

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Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
Network-on-Chip (NoC) communication architectures are increasingly being used today to interconnect cores on Chip Multi-Processors (CMPs). Permanent faults in NoCs due to fabrication challenges in Ultra Deep Sub-Micron (UDSM) technology nodes and due to wearout have led to an increased emphasis on fault tolerant design techniques. To ensure fault tolerant communication in NoCs, several fault tolerant routing algorithms have been proposed in recent years with the goal of routing flits around faults. A majority of these algorithms are based on the turn model approach due to its simplicity and inherent freedom from deadlock.
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