Institute of Electrical & Electronic Engineers
Testing of high density SoCs operating at high clock speeds is an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when the chip works at normal operating speed. In this paper, the authors propose a methodology for at speed testing of delay faults in links connecting two distinct clock domains in a SoC. They give an analytical analysis about the efficiency of this method. They also propose a simple digital hardware structure for the receiver end of the link under test to detect delay faults.