International Journal of Scientific & Technology Research
An on-chip calibration technique has been proposed for a 7-bit Comparator based Asynchronous Binary Search (CABS) A/D converter. The proposed design is verified using an 8-bit, 3.3V, 10 MS/s asynchronous SAR A/D converter by integrating the calibration scheme into the A/D converter. The 8-bit asynchronous SAR A/D converter consists of a track-and-hold followed by a two-step conversion process. The two-step architecture consists of a 1-bit course and a 7-bit fine converter. The 1-bit coarse converter is implemented using the SAR-CC principle and the 7-bit fine converter is implemented using the CABS principle.