On-Chip Networks from a Networking Perspective: Congestion and Scalability in Many-Core Interconnects

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Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
In this paper, the authors present Network-on-Chip (NoC) design and contrast it to traditional network design, highlighting similarities and differences between the two. As an initial case study, they examine network congestion in bufferless NoCs. They show that congestion manifests itself differently in a NoC than in traditional networks. Network congestion reduces system throughput in congested workloads for smaller NoCs (16 and 64 nodes), and limits the scalability of larger bufferless NoCs (256 to 4096 nodes) even when traffic has locality (e.g., when an application's required data is mapped nearby to its core in the network).
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