On-Chip Permutation Network for Multiprocessor System-on-Chip
The novel on-chip network in silicon proven design to support guaranteed traffic permutation in multiprocessor SoC applications. A pipelined circuit-switching employed in the proposed network with FIFO approach combined with a multistage for arbitrary permutations. The dynamic path-setup scheme enables runtime path arrangement for arbitrary traffic permutations. The circuit switching approach offers the permuted data and its compact overhead enables the benefit of stacking multiple networks in system on chip. A CMOS test-chip with 0.13m validates the feasibility and efficiency of the proposed design.