On-Chip Source Synchronous Interface Timing Test Scheme with Calibration

Provided by: European Design and Automation Association
Topic: Hardware
Format: PDF
In this paper, the authors present an on-chip test circuit with a high resolution for testing source synchronous interface timing. Instead of a traditional strobe-scanning method, an on-chip delay measurement technique which detects the timing mismatches between data and clock paths is developed. Using a programmable pulse generator, the timing mismatches are detected and converted to pulse widths. To obtain digital test results compatible with low-cost ATE, an Analog-to-Digital Converter (ADC) is used. They propose a novel calibration method for the input range for the ADC using a binary search algorithm.

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