On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
In this paper, the authors present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algorithm even if basic network problems such as deadlock and livelock, are considered. They develop a new packet definition to support different requirements in an MIMD message passing architecture and also verify its efficiency by comparing simulation results with various routing algorithms. Major contributions of this paper are the design of Network-on-Chip (NoC) architecture adopting a minimal adaptive routing algorithm with competitive performance and feasible design complexity, thus satisfying all the stated design goals.

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