On Supporting Rapid Exploration of Memory Hierarchies Onto FPGAs
In this paper, the authors introduce a novel methodology for enabling fast yet accurate exploration of memory organizations onto FPGA (Field Programmable Gate Array) devices. The proposed methodology is software supported by a new open-source tool framework, named NAROUTO. This framework is the only public available solution for performing architecture-level exploration, as well as application mapping onto FPGA devices with different memory organizations; under a variety of design criteria (e.g. delay improvement, power optimization, area savings, etc.). Experimental results with a number of industrial oriented kernels prove the efficiency of the proposed solution, as compared to similar approaches.