Static Random Access Memory (SRAM) is a critical part of most VLSI System-on-Chip (SoC) applications. The SRAM bit cell design has to cope with stringent requirement on the cell area leading to minimum (or close to minimum) sized transistors. Due to this scaling trend, device variations and leakage are increasing sharply with each shrinking technology node. Further, the supply voltage is scaled down to reduce dynamic and leakage power consumption. The operation of the SRAM at lower supply voltage becomes even more challenging.