On-the-fly Data Transmission for FPGA Acceleration: A Case Study

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Provided by: AICIT
Topic: Hardware
Format: PDF
FPGA modules may have rather high speed up ratios over CPUs, but they can rarely achieve the best performance due to communication bottlenecks in low coupling reconfigurable systems. In this paper, the authors adopt a fast-speed data transmission method to increase the capacity of hardware acceleration. On receiving a frame, the FPGA computes and sends back the result on the fly, rather than waiting until the whole frame received. They implemented a Triple DES application as a case study, using Gigabit Ethernet.
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