On the Hardware Reduction of Z-Datapath of Vectoring CORDIC

In this paper, the authors present a novel design of a hardware optimal vectoring CORDIC processor. They present a mathematical theory to show that using bipolar binary notation it is possible to eliminate all the arithmetic computations required along the z-datapath. Using this technique it is possible to achieve three and 1.5 times reduction in the number of registers and adder respectively compared to classical CORDIC. Following this, a 16-bit vectoring CORDIC is designed for the application in Synchronizer for IEEE 802.11a standard.

Provided by: University of South Florida Topic: Hardware Date Added: Oct 2006 Format: PDF

Find By Topic