On the Implementation of a Three-Operand Multiplier

Provided by: University of California, Los Angeles (Anderson)
Topic: Hardware
Format: PDF
Much research has been done in the design of multioperand addition and in parallel multiplication. In, the concepts of multi-operand addition and parallel multiplication are combined, and a new scheme is presented for the design of fast multi-operand multiplication. A new approach for a three-operand multiplier is proposed, using initial two-level Radix-4 recoding, in order to reduce the cost and delay of other utilized methods. A three-operand 4-bit multiplier is demonstrated as a model, and serves as a building block for three-operand multipliers of higher precision. The proposed method is shown to yield a significant reduction in both the cost and delay of a three-operand 4-bit multiplier.

Find By Topic