International Journal of Advanced Research in Computer Science and Software Engineering (IJARCSSE)
Formal verification requires the users' to think differently. For example, simulation is empirical i.e. they use trial and error to try to uncover bugs that can take an intractable amount of time to try all possible combinations. Hence, it is never complete. Furthermore, since engineers have to define and generate a significant number of input scenarios, they are focusing their effort on how to break the design not on what the design is supposed to do. Formal verification, on the other hand, is mathematical, exhaustive and allows the engineer to focus solely on intent or \"What is the design's correct behaviour?\" Formal verification is the process of proving or disproving properties using formal methods (i.e., mathematically precise, algorithmic methods).