Optimal Loop-Unrolling Mechanisms and Architectural Extensions for an Energy-Efficient Design of Shared Register Files in MPSoCs

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Provided by: Universidad Panamericana, Campus Guadalajara
Topic: Hardware
Format: PDF
Business analysts forecast a 200 billion dollar market for System-on-Chip (SoC) media-rich, mobile wireless terminals in the near future. In this paper the authors introduce a new hardware/software approach to reduce the energy of the shared register file in upcoming embedded architectures with several VLIW processors. This paper includes a set of architectural extensions and special loop unrolling techniques for the compilers of MPSoC platforms. This complete hardware/software support enables reducing the energy consumed in the register file of MPSoC architectures up to a 60% without introducing performance penalties.
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