Optimal Placement-Aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators

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Provided by: National University of Singapore
Topic: Hardware
Format: PDF
Modern use of FPGAs as hardware accelerators involves the partial reconfiguration of hardware resources as the application executes. In this paper, the authors present a polynomial time algorithm for scheduling reconfiguration tasks given a trace of actors (invocations of hardware kernels) that is both provably optimal and placement-aware. In addition, they will propose a dependence analysis to determine whether for each actor instance, a reconfiguration task is needed prior to its execution in hardware. A case study using the H.264 encoder is presented to compare their algorithm against the state-of-the-art heuristics.
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