Networks-on-Chip (NoC) way of system design has been introduced to overcome the communication and the performance bottlenecks of a bus based system design. Area is at a premium in FPGAs. In this paper, the authors propose to reduce network area overhead by reducing the number of routers, by making the router handle multiple logic cores. They implement an improved multi-local port router design with variable number of local ports. In addition to substantial area savings, they observe significant performance improvement. They discuss the issues involved in the use of multi-local port routers for NoC design in FPGAs.