Optimization of Delay and Energy in On-Chip Buses Using Bus Encoding Technique

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Provided by: International Journal of Computer Applications
Topic: Hardware
Format: PDF
In Very Deep Sub-Micron (VDSM) fault-tolerant busses, crosstalk noise and logic faults caused due to shrinking wire-size and reduced inter-wire spacing are major factors affecting the performance of on-chip interconnects, such as high power consumption and increased delay. In this paper, the authors propose a bus optimization technique which reduces the energy and power-delay using hamming single error correcting code. In this coding scheme, they implement Fibonacci representation of optimal (7, 4) hamming code which is more efficient than single error correction (9, 4) hamming code.
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