Optimization of Fault Tolerant Circuits on SRAM-Based FPGAs

In this paper the authors propose an efficient design approach for testing, detecting and tolerating single stuck at faults (s-a-0, s-a-1) at the interconnect levels at the output of any digital circuit under test. Compared to alternate designs, the one presented here allows achieving fault tolerance at lower design costs. In this approach the authors have used full adder two full adder out of which one of the considered as reference case of occurrence of stuck-at-faults at any interconnect, the circuit will reconfigure itself to select the other fault free output available on another interconnect, e.g., if s1/c1 (of fa1) is stuck at any fault then circuit will choose s2 /c2 (of fa2) as the output which is fault free.

Provided by: IJCITB Topic: Storage Date Added: Jun 2012 Format: PDF

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