Provided by: International Journal & Magazine of Engineering, Technology, Management And Research (IJMETMR)
Date Added: Dec 2014
In modern day, embedded memory density and area on-chip is increasing, it is essential to define new test algorithms which fulfill the need of detecting new faults. The existing March algorithms consist of as many as four or seven operations per March element. In this paper, the authors have presented an optimization of architecture which can implement these new March BLC tests having number of operations per element according to the today's growing needs of embedded memory testing with enhanced fault using Verilog HDL as a primary language and used Modelsim SE 6.5 f as simulation tool.