Optimization of Power for Sequential Elements in Pulse Triggered Flip-Flop Using Low Power Topologies

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Provided by: International Journal of Scientific & Technology Research
Topic: Hardware
Format: PDF
The choice of flip-flop technologies is an essential importance in design of VLSI integrated circuits for high speed and high performance CMOS circuits. This paper is to design a low-power pulse-triggered flip-flop. Flip-flops are the major storage elements in all SOC's of digital design. They accommodate most of the power that has been applied to the chip. Flip-flop is one of the most power consumption components. It is important to reduce the power dissipation in both clock distribution networks and flip-flops. The power delay is mainly due to the clock delays.
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