The popularity of multiprocessors over the last few years has been made possible by Network-on-Chip (NoC). The advent of Three-Dimensional Network-on-Chip (3D NoC) has facilitated the communication in Three-Dimensional Integrated Circuits (3D IC). However, the implementation of 3D NoC is a vital issue with the fabrication of Through-Silicon-Via (TSV), due to its effects on chip yield and area occupied. Hence, this paper focuses on the reduction of TSV. The optimum number of TSV results in an improved yield with reduced TSV area.