Multiplication is the commonly used operations in a Central Processing Unit (CPU). The performance of the CPU depends on multiplier which may be slower and may consume significant amount of power. This paper presents a low power and high speed multiplier architecture using Vedic mathematics technique. The paper also proves the efficiency of Urdhava Tiryakbhyam sutra of Vedic mathematics which shows a difference between actual process of multiplication and Vedic multiplication. Carry Save Adder (CSA) is used in the architecture to have reduced delay.