Optimized Multiplier using Reversible Logic Gates: A Vedic Mathamatical Approach

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Provided by: International Journal of Advanced Research in Computer Engineering & Technology
Topic: Hardware
Format: PDF
Multipliers are major components of any processor or computing machine. Digital Signal Processors (DSPs) and performance of microcontrollers are evaluated on the basis of number of multiplications performed at unit time. Hence multiplier architectures are bound to increase the efficiency of the system. Vedic mathematics is one of the multiplier algorithms to perform multiplication operation. It is simple architecture with increased speed forms an unparalleled combination for serving any complex multiplication computations. With these additional highlights, implementing multiplier using reversible logic and further reduces power dissipation.
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