Optimized Reconfigurable ASIP of FIR Filter using FPGA
Reconfigure ability denotes reconfigurable computing capabilities of a system, so that its behavior can be changed by reconfiguration with improvements in capacity & performance. Application specific instruction set processor is bridge between ASIC & DSP. This research works based on Xilinx system generator which support for runtime reconfiguration which further controls ASIP. FIR (Finite Impulse Response) filter is configured for different taps & methods.1-D signal i.e., ECG (ElectroCardioGram) is taken for filtration, which having gaussian noise also known as EMG noise.