Optimizing Communication and Capacity in a 3D Stacked Reconfigurable Cache Hierarchy

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Provided by: The University of Tulsa
Topic: Storage
Format: PDF
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, the authors postulate a 3D chip design that stacks SRAM and DRAM upon processing cores and employs OS-based page coloring to minimize horizontal communication of cache data. They then propose a heterogeneous reconfigurable cache design that takes advantage of the high density of DRAM and the superior power/delay characteristics of SRAM to efficiently meet the working set demands of each individual core.
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