Optimizing Data Flow Graphs to Minimize Hardware Implementation

Provided by: edaa
Topic: Hardware
Format: PDF
Many computations encountered in high-level design specifications are represented as polynomial expressions. They are used in computer graphics designs and Digital Signal Processing (DSP) applications, where designs are specified as algorithms written in C/C++. This paper describes an efficient graph-based method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, Common Subexpression Elimination (CSE) and decomposition of algebraic expressions performed on a canonical representation, Taylor expansion diagram. The method is generic, applicable to arbitrary algebraic expressions and does not require specific knowledge of the application domain.

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