Optimizing Decomposition-Based Packet Classification Implementation on FPGAs
Hardware implementations of Internet Protocol (IP) classification algorithms have been proposed by the research community over the years to realize high speed routers and Internet backbone. Decomposition-based IP classification algorithms are desirable for hardware implementation due to their parallel search on multiple fields. These algorithms consist of two phases: independent searches on each packet field in the first phase followed by the second phase where the results from the first phase are combined. However, the primary challenge in implementing this high-level approach lies in the second phase, i.e. how to efficiently combine the results of the single field searches.