Optimizing Instruction-Set Extensible Processors Under Data Bandwidth Constraints

Provided by: edaa
Topic: Hardware
Format: PDF
The authors present a methodology for generating optimized architectures for data bandwidth constrained extensible processors. They describe a scalable Integer Linear Programming (ILP) formulation, that extracts the most profitable set of instruction-set extensions given the available data bandwidth and transfer latency. Unlike previous approaches, they differentiate between number of inputs and outputs for instruction-set extensions and the number of register le ports. This differentiation makes their approach applicable to architectures that include architecturally visible state registers and dedicated data transfer channels.

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