Optimizing SDRAM Bandwidth for Custom FPGA Loop Accelerators

Provided by: Association for Computing Machinery
Topic: Storage
Format: PDF
Memory bandwidth is critical to achieving high performance in many FPGA applications. The bandwidth of SDRAM memories are, however, highly dependent upon the order in which addresses are presented on the SDRAM interface. The authors present an automated tool for constructing an application specific on-chip memory address sequencer which presents requests to the external memory with an ordering that optimizes off-chip memory bandwidth for fixed on-chip memory resource. Within a class of algorithms described by affine loop nests, this approach can be shown to reduce both the number of requests made to external memory and the overhead associated with those requests.

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