Optimizing Throughput of Power-And Thermal-Constrained Multicore Processors Using DVFS and Per-Core Power-Gating

Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
Process variability from a range of sources is growing as technology scales below 65nm, resulting in increasingly non-uniform transistor delay and leakage power both within a die and across dies. As a result, the negative impact of process variations on the maximum operating frequency and the total power consumption of a processor is expected to worsen. Meanwhile, manufacturers have integrated more cores in a single die, substantially improving the throughput of a processor running highly-parallel applications. However, many existing applications do not have high enough parallelism to exploit multiple cores in a die.

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