Optimizing Throughput/Power Trade-Offs in Hardware Transactional Memory Using DVFS and Intelligent Scheduling

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Provided by: Association for Computing Machinery
Topic: Storage
Format: PDF
Power has emerged as a first-order design constraint in modern processors and has energized microarchitecture researchers to produce a growing number of power optimization proposals. Almost in tandem with the move toward more energy-efficient designs, architects have been increasing the number of Processing Elements (PEs) on a single chip and promoting the concept of running multithreaded workloads. Nevertheless, software is still lagging behind and is often unable to exploit these additional resources - giving rise to transactional memory.
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