Optimizing Two-Dimensional DMA Transfers for Scratchpad Based MPSoCs Platforms

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Provided by: Reed Business Information
Topic: Big Data
Format: PDF
Reducing the effects of off-chip memory access latency is a key factor in exploiting efficiently embedded multi-core platforms. The authors consider architectures that admit a multi-core computation fabric, having its own fast and small memory to which the data blocks to be processed are fetched from external memory using a DMA (Direct Memory Access) engine, employing a double- or multiple-buffering scheme to avoid processor idling. In this paper they focus on application programs that process two-dimensional data arrays and they determine automatically the size and shape of the portions of the data array which are subject to a single DMA call, based on hardware and applications parameters.
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